1. Field of the Invention
The present invention relates to multiplexers. More particularly, the present invention relates to apparatus and methods for improving the performance of wide multiplexer structures.
2. Description of Related Art
It is frequently advantageous in the electronic arts to be able to connect a wide bus (i.e., one having more than one line) to a single line bus. A structure to effect such a connection is shown in FIG. 1. Specifically, in FIG. 1 there is shown a structure (generally designated by reference numeral 10) for connecting an bus having "n" lines to a bus having only one line. The individual lines of the n line bus shown in FIG. 1 are designated X0, X1, X2 . . . Xn-1. The line bus shown in FIG. 1 is simply designated Y.
Continuing to refer to FIG. 1, it may be seen that the structure 10 comprises n transistors (each designated by reference numeral 12), one each for each line of the n line bus. In structure 10, a single bit of data effectively controls each of the n transistors 12. These bits are depicted in FIG. 1 in the form of memory bit boxes (each designated by reference numeral 14), each of which is connected to the gate of an associated transistor 12. Each of the bits in the "memory cells" 14 may be enabled, therefore allowing connection of the associated X and the Y line (e.g., enabling memory bit 0 allows connection of line X0 and the Y line) and transmission of data on the relevant X line to the Y line (e.g., X0 to Y in the example being presented).
The structure depicted in FIG. 1 has certain shortcomings, however. It is possible, for example, if any two of the memory cells are on and if they differ, line Y can be in an unknown state. More specifically, as an example, X0 and X1 could differ. If, in such a case, both memory bits 0 and 1 were enabled, the value on line Y would be unknown. Further, there would exist a high current path between lines X0 and X1 in such a case, assuming that both transistors T0 and T1 were enabled and that the transistors were of relatively large values for speed.
Based upon the foregoing, those skilled in the art should recognize and appreciate the shortcomings and deficiencies of prior art structures such as that depicted in FIG. 1.